Method for avoiding short-circuit of conductive wires

ABSTRACT

A method for avoiding short circuits of conductive wires is provided. The method includes the following steps: A substrate having a contact area is provided. A first opening is formed in the substrate to expose the contact area. The first opening is filled with a first conductive material to form a first conductive layer. A portion of the first conductive layer is removed to form a second opening for exposing a sidewall of the substrate. A spacer is formed on the sidewall. The second opening is filled with a second conductive material to form a second conductive layer. A patterned dielectric layer is formed over the substrate. The patterned dielectric layer defines a wire opening to expose the second conductive layer. The wire opening is filled with a third conductive material to form a wire electrically contacting the second conductive layer.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority to Taiwan Patent Application No.092121411 filed Aug. 5, 2003.

FIELD OF THE INVENTION

The present invention provides a method for avoiding short circuits ofconductive wires, and more particularly, of conductive wires insemiconductor processes.

BACKGROUND OF THE INVENTION

With the growth of industrial technology, the dimension of semiconductorprocess gets smaller and smaller to satisfy the requirement of more andmore complex ultra large-scale integration. The problem coming alongwith smaller critical dimension is that short-circuits among wireshappen more easily, and the problem seriously affects the yield and thereliability of the integration. Especially in the complex integration,the wires and contacts made by etching and deposition (for example,bit-line contacts) have short-circuit problems due to minor differenceoccurring while having the insufficient process window during theprocess.

FIG. 1 shows a top view of the wires and bit-line contacts of prior art.FIG. 1 shows the relative location of a gate 103, a wire 105 and abit-line contact 101. The profile of I-I′ section is shown in FIG. 2.FIG. 2 shows a profile of the wires and bit-line contacts of prior art.In FIG. 2, on the semiconductor substrate 201 is an insulation layer203, which has a predetermined opening and the conductive layer is inthe opening. As shown in FIG. 2, there are the wires 105 on theconductive layer 205 and the insulation layer 203 after the metallicdeposition. The short-circuit problem happens after the wire 105deposition if an improper etching process generates an over-scale trench(Illustrated in FIG. 2).

SUMMARY OF THE INVENTION

The present invention provides a method for avoiding short circuits ofconductive wires. The method of the present invention includes a spacerprocess to avoid contact between the wires and the bit-line contact toincrease the yield.

The present invention provides a method for avoiding short circuits ofconductive wires, and more particularly, for avoiding short-circuit ofbit-line contacts and the wires in semiconductor process.

The methods of the present invention are described as follows. Asubstrate having a contact area is provided. A first opening is formedin the substrate to expose the contact area. The first opening is filledwith a first conductive material to form a first conductive layer. Aportion of the first conductive layer is removed to form a secondopening for exposing a sidewall of the substrate. A spacer is formed onthe sidewall. The second opening is filled with a second conductivematerial to form a second conductive layer. A patterned dielectric layeris formed over the substrate. The patterned dielectric layer defines awire opening to expose the second conductive layer. The wire opening isfilled with a third conductive material to form a wire electricallycontacting the second conductive layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a top view of the wires and bit-line contacts of the priorart.

FIG. 2 shows a profile of the wires and bit-line contacts of the priorart.

FIG. 3 a shows a profile of the embodiment of the present invention.

FIG. 3 b shows a profile of the embodiment of the present invention.

FIG. 3 c shows a profile of the embodiment of the present invention.

FIG. 3 d shows a profile of the embodiment of the present invention.

FIG. 3 e shows a profile of the embodiment of the present invention.

FIG. 3 f shows a profile of the embodiment of the present invention.

FIG. 3 g shows a profile of the embodiment of the present invention.

FIG. 3 h shows a profile of the embodiment of the present invention.

FIG. 3 i shows a profile of the embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides a method for avoiding short circuits ofconductive wires. The preferred embodiment of the present invention isthe wires of the semiconductor component, for example, the wires andbit-line contacts of dynamic random access memory. Besides, the methodcan be applied to other processes to solve the short-circuit problem.

FIG. 3 a shows a profile of the embodiment of the present invention. Asubstrate 300 includes a semiconductor substrate 301 having a contactarea 33 and an insulation layer 303 on it. The substrate 300 is providedfor the manufacture of the integration components.

FIGS. 3 b-3 e show profiles of the embodiment of the present invention,and the order of the Figs follows the process sequence. As FIG. 3 bshows, a first opening 31 is formed at the insulation layer 303 of thesubstrate 300 to expose the contact area 33. The contact area 33 couldbe a bit-line contact area. The mentioned opening can be formed byphotolithography and etching. The first opening 31 is used fordeposition of conductive layer follow up, and the disposition isdetermined by the design. The steps forming the first opening 31includes: forming a patterned photoresist layer on the insulation layer303, the patterned photoresist layer defining the first opening 31;using the photoresist layer as a mask to etch the insulation layer 303to expose the bit-line contact area 33.

As FIG. 3 c shows, filling the first opening 31 with a first conductivematerial to form a first conductive layer 305 electrically connecting tothe contact area 33. The first conductive material could be poly-siliconor other similar substances. The steps forming the first conductivelayer 305 include: depositing a poly-silicon layer over the substrate300 and filling the first opening 31.

Then, as FIG. 3 d shows, removing a portion of the first conductivelayer 305 to form a second opening 32 for exposing a sidewall 34 of thesubstrate 300. The way to form the second opening 32 could be etchingback the first conductive layer 305 to expose the sidewall 34 of thesubstrate 300.

As FIG. 3 e shows, a spacer 307 is formed on the sidewall 34. The spacer307 could be made of nitride oxide or other similar substances. Thesteps forming the spacer 307 include: forming a conformal dielectriclayer over the substrate 300, and anisotropically etching the conformaldielectric layer to form the spacer 307 on the sidewall 34.

As FIG. 3 f shows, the second opening 32 is filled with a secondconductive material to form a second conductive layer 309. The secondconductive material could be poly-silicon or other similar substances.The steps forming the second conductive layer 309 include: depositing apoly-silicon layer over the substrate 300, filling the second opening 32with the poly-silicon layer, and etching back the poly-silicon layer toexpose a portion of the spacer 307.

As FIG. 3 g shows, forming a dielectric layer 313 over the substrate 300and the second conductive layer 309, and forming a patterned photoresist317 on the dielectric layer 313.

As FIG. 3 h shows, the patterned photoresist 317 defines a wire opening319. The pattern photoresist 317 is used as a mask and the dielectriclayer 313 is etched corresponding to the second conductive layer 309 toexpose the second conductive layer 309. In other wires positions notcontacting the bit-line contact, the dielectric layer 313 and a portionof the insulation layer 303 are also etched. The patterned photoresist317 is removed to form the patterned dielectric layer 313. In thementioned method, we can planarize the dielectric layer 313 by thechemical-mechanical polishing method before the patterned photoresist317 is formed.

As FIG. 3 i shows, the wire opening 319 is filled with a thirdconductive material to form the wires 311 and 315. The wire 311electrically contacts the second conductive layer 309 and the number ofthe wires 311 can be designed to satisfy users' demands. The thirdconductive material can be wolfram or other similar metals. The stepsforming the wire include: forming a metallic layer over the patterneddielectric layer 313, filling the wire opening 319, and planarizing themetallic layer to form the wires 311 and 315.

As shown in FIG. 3 i, the first conductive layer 305 is electricallyconnected to the second conductive layer 309 in this embodiment andtogether they form a bit-line contact. The spacer 307 of the presentinvention can increase the distance between the wire 315 and thebit-line contact to avoid short circuits effectively.

While the invention has been described in connection with what ispresently considered to be the most practical and preferred embodiments,it is to be understood that the invention is not to be limited to thediscovered embodiments. The invention is intended to cover variousmodifications and equivalent arrangement included within the spirit andscope of the appended claims.

1. A method for avoiding short-circuit of conductive wires, comprising:providing a substrate having a contact area; forming a first opening inthe substrate to expose the contact area; filling the first opening witha first conductive material to form a first conductive layer; removing aportion of the first conductive layer to form a second opening forexposing a sidewall of the substrate; forming a spacer on the sidewall;filling the second opening with a second conductive material to form asecond conductive layer; forming a patterned dielectric layer over thesubstrate, the patterned dielectric layer defining a wire opening toexpose the second conductive layer; and filling the wire opening with athird conductive material to form a wire electrically contacting thesecond conductive layer.
 2. The method of claim 1, wherein the substrateincludes a semiconductor substrate and an insulation layer, and thecontact area is a bit-line contact area.
 3. The method of claim 2,wherein the step of forming the first opening includes: forming apatterned photoresist layer on the insulation layer, the patternedphotoresist layer defining the first opening; and using the photoresistlayer as a mask to etch the insulation layer to expose the bit-linecontact area.
 4. The method of claim 1, wherein the step of forming thefirst conductive layer includes: depositing a poly-silicon layer overthe substrate, and the first opening is filled with the poly-siliconlayer.
 5. The method of claim 4, wherein the step of forming the secondopening includes: etching back the poly-silicon layer to expose thesidewall of the substrate.
 6. The method of claim 1, wherein the step offorming the spacer includes: forming a conformal dielectric layer overthe substrate; and anisotropically etching the conformal dielectriclayer to form the spacer on the sidewall.
 7. The method of claim 1,wherein the step of forming the second conductive layer includes:depositing a poly-silicon layer over the substrate, and the secondopening is filled with the poly-silicon layer; and etching back thepoly-silicon layer to expose a portion of the spacer.
 8. The method ofclaim 1, wherein the step of forming the patterned dielectric layerincludes: forming a dielectric layer over the substrate and the secondconductive layer; forming a patterned photoresist on the dielectriclayer, the patterned photoresist defining the wire opening; using thepattern photoresist as a mask to etch the dielectric layer to expose thesecond conductive layer; and removing the patterned photoresist to formthe patterned dielectric layer.
 9. The method of claim 8, wherein thestep of forming the patterned dielectric layer includes: planarizing thedielectric layer by a chemical-mechanical polishing method.
 10. Themethod of claim 8, wherein the step of forming the wire includes:forming a metallic layer over the patterned dielectric layer and fillingthe wire opening; and planarizing the metallic layer to form the wire.11. A method for avoiding short-circuit of conductive wires, comprising:providing a substrate having a contact area; forming a first opening inthe substrate to expose the contact area; filling the first opening witha first conductive material to form a first conductive layer; removing aportion of the first conductive layer to form a second opening forexposing a sidewall of the substrate; forming a spacer on the sidewall;filling the second opening with a second conductive material to form asecond conductive layer; forming a patterned dielectric layer over thesubstrate, the patterned dielectric layer defining a plurality of wireopenings to expose the second conductive layer and a portion of thesubstrate; and filling the plurality of wire openings with a thirdconductive material to form a plurality of wires, at least one of theplurality of wires electrically contacting the second conductive layer,and at least one of the plurality of wires electrically insulating thesecond conductive layer.
 12. The method of claim 11, wherein thesubstrate includes a semiconductor substrate and an insulation layer,and the contact area is a bit-line contact area.
 13. The method of claim12, wherein the step of forming the first opening includes: forming apatterned photoresist layer on the insulation layer, the patternedphotoresist layer defining the first opening; and using the photoresistlayer as a mask to etch the insulation layer to expose the bit-linecontact area.
 14. The method of claim 11, wherein the step of formingthe first conductive layer includes: depositing a poly-silicon layerover the substrate, and fill the first opening is filled with thepoly-silicon layer.
 15. The method of claim 14, wherein the step offorming the second opening includes: etching back the poly-silicon layerto expose the sidewall of the substrate.
 16. The method of claim 1wherein the step of forming the spacer includes: forming a conformaldielectric layer over the substrate; and anisotropically etching theconformal dielectric layer to form the spacer on the sidewall.
 17. Themethod of claim 11, wherein the step of forming the second conductivelayer includes: depositing a poly-silicon layer over the substrate, andthe second opening is filled with the poly-silicon layer; and etchingback the poly-silicon layer to expose a portion of the spacer.
 18. Themethod of claim 11, wherein the step of forming the patterned dielectriclayer includes: forming a dielectric layer over the substrate and thesecond conductive layer; forming a patterned photoresist on thedielectric layer, the patterned photoresist defining the plurality ofwire openings; using the pattern photoresist as a mask to etch thedielectric layer and the substrate to expose the second conductive layerand the portion of the substrate; and removing the patterned photoresistto form the patterned dielectric layer.
 19. The method of claim 18,wherein the step of forming the patterned dielectric layer includes:planarizing the dielectric layer by a chemical-mechanical polishingmethod.
 20. The method of claim 18, wherein the step of forming the wireincludes: forming a metallic layer over the patterned dielectric layerand filling the plurality of wire openings; and planarizing the metalliclayer to form the plurality of wires.